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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a cmos 80 mhz monolithic 256 3 24(18) color palette ram-dacs adv478/adv471 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram features personal system/2* compatible 80 mhz pipelined operation triple 8-bit (6-bit) d/a converters 256 3 24(18) color palette ram 15 3 24(18) overlay registers rs-343a/rs-170 compatible outputs sync on all three channels programmable pedestal (0 or 7.5 ire) external voltage or current reference standard mpu interface +5 v cmos monolithic construction 44-pin plcc package power dissipation: 800 mw applications high resolution color graphics cae/cad/cam applications image processing instrumentation desktop publishing available clock rates 80 mhz 66 mhz 50 mhz 35 mhz general description the adv478 (adv?) and adv471 are pin compatible and software compatible ram-dacs designed specifically for personal system/2 compatible color graphics. the adv478 has a 256 24 color lookup table with triple 8-bit video d/a converters. it may be configured for either 6 bits or 8 bits per color operation. the adv471 has a 256 18 color lookup table with triple 6-bit video d/a converters. options on both parts include a programmable pedestal (0 or 7.5 ire) and use of an external voltage or current reference. adv is a registered trademark of analog devices, inc. * personal system/2 is a trademark of international business machines corp. fifteen overlay registers provide for overlaying cursors, grids, menus, ega emulation, etc. also supported is a pixel read mask register and sync generation on all three channels. the adv478 and adv471 generate rs-343a compatible video signals into a doubly terminated 75 w load, and rs-170 compatible video signals into a singly terminated 75 w load, without requiring external buffering. differential and integral linearity errors are guaranteed to be a maximum of 1 lsb for the adv478 and 1/4 lsb for the adv471 over the full tem- perature range. obsolete
rev. b adv478/adv471Cspecifications parameter all versions units test conditions/comments static performance resolution (each dac) 3 8 (6) bits accuracy (each dac) 3 integral nonlinearity 1 (1/4) lsb max differential nonlinearity 1 (1/4) lsb max guaranteed monotonic gray scale error 5 % gray scale max coding binary digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i in 1 m a max v in = 0.4 v or 2 .4 v input capacitance, c in 7 pf max digital outputs output high voltage, v oh 2.4 v min i source = 400 m a output low voltage, v ol 0.4 v max i sink = 3.2 ma floating-state leakage current 50 m a max floating-state output capacitance 7 pf max analog outputs gray scale current range 20 ma max output current white level relative to blank 17.69 ma min typically 19.05 ma 20.40 ma max white level relative to black 16.74 ma min typically 17.62 ma 18.50 ma max black level relative to blank 0.95 ma min typically 1.44 ma (setup = v aa ) 1.90 ma max black level relative to blank 0 m a min typically 5 m a (setup = gnd) 50 m a max blank level 6.29 ma min typically 7.62 ma 8.96 ma max sync level 0 m a min typically 5 m a 50 m a max lsb size 3 69.1 (279.68) m a typ 8/ 6 = logical 1 for adv478 dac to dac matching 5 % max typically 2% output compliance, v oc C1 v min +1.5 v max output impedance, r out 10 k w typ output capacitance, c out 30 pf max i out = 0 ma voltage reference voltage reference range, v ref 1.14/1.26 v min/v max input current, i vref 10 m a typ tested in voltage reference configuration with v ref = 1.235 v power supply supply voltage, v aa 4.75/5.25 v min/v max 80 mhz and 66 mhz parts 4.50/5.50 v min/v max 50 mhz and 35 mhz parts supply current, i aa 220 ma max typically 180 ma power supply rejection ratio 0.5 %/% max f = 1 khz, comp = 0.1 m f power dissipation 1100 mw max typically 900 mw, v aa = 5 v dynamic performance clock and data feedthrough 4, 5 C30 db typ glitch impulse 4, 5 75 pv secs typ dac to dac crosstalk 6 C23 db typ notes 1 5% for 80 mhz and 66 mhz parts; 10% for 50 mhz and 35 mhz parts. 2 temperature range (t min to t max ); 0 c to +70 c. 3 numbers in parentheses indicate adv471 parameter value. 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. for this test, the digital inputs have a 1 k w resistor to ground and are driven by 74hc logic. glitch impulse includes clock and data feedthrough, C3 db test bandwidth = 2 clock rate. 5 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and out- puts. analog output load 10 pf, d0Cd7 output load 50 pf. see timing notes in figure 2. 6 dac to dac crosstalk is measured by holding one dac high while the other two are making low to high and high to low transitions. specifications subject to change without notice. (v aa 1 = +5 v, setup = 8/ 6 = v aa , v ref = +1.235 v. r set = 147 v . all specifications t min to t max 2 unless otherwise noted.) C2C obsolete
adv478/adv471 C3C rev. b timing characteristics 1 parameter kp80 version kp66 version kp50 version kp35 version units conditions/comments f max 80 66 50 35 mhz clock rate t 1 10 10 10 10 ns min rs0Crs2 setup time t 2 10 10 10 10 ns min rs0Crs2 hold time t 3 5555ns min rd asserted to data bus driven t 4 40 40 40 40 ns max rd asserted to data valid t 5 20 20 20 20 ns max rd negated to data bus 3-stated t 6 10 10 10 10 ns min write data setup time t 7 10 10 10 10 ns min write data hold time t 8 50 50 50 50 ns min rd , wr pulse width low t 9 6 t 12 6 t 12 6 t 12 6 t 12 ns min rd , wr pulse width high t 10 3333ns min pixel and control setup time t 11 3333ns min pixel and control hold time t 12 12.5 15.3 20 28 ns min clock cycle time t 13 4567ns min clock pulse width high time t 14 4569ns min clock pulse width low time t 15 30 30 30 30 ns max analog output delay t 16 3333ns typ analog output rise/fall time t 17 4 13 15.3 20 28 ns typ analog output settling time t 18 2222ns max analog output skew t pd 4 t 12 4 t 12 4 t 12 4 t 12 ns min pipeline delay notes 1 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf, 37.5 w . d0Cd7 output load 50 pf. see timing notes in figure 2. 2 5% for 80 mhz and 66 mhz parts; 5% for 50 mhz and 35 mhz parts. 3 temperature range (t min to t max ); 0 c to +70 c. 4 settling time does not include clock and data feedthrough. for this test, the digital inputs have a 1 k w resistor to ground and are driven by 74hc logic. specifications subject to change without notice timing diagrams figure 1. mpu read/write timing figure 2. video input/output timing (v aa 2 = +5 v, setup = 8/ 6 = v aa , v ref = 1.235 v. r set = 147 v . all specifications t min to t max 3 .) obsolete
adv478/adv471 C4C rev. b recommended operating conditions parameter symbol min typ max units power supply v aa 80 mhz, 66 mhz parts 4.75 5.00 5.25 volts 50 mhz, 35 mhz parts 4.5 5.00 5.5 volts ambient operating temperature t a 0 +70 c output load r l 37.5 w voltage reference configuration reference voltage v ref 1.14 1.235 1.26 volts current reference configuration reference current i ref C3 C10 ma ordering guide temperature color palette package model range ram speed option* adv471kp80 0 c to +70 c 256 18 80 mhz p-44a adv471kp66 0 c to +70 c 256 18 66 mhz p-44a adv471kp50 0 c to +70 c 256 18 50 mhz p-44a adv471kp35 0 c to +70 c 256 18 35 mhz p-44a adv478kp80 0 c to +70 c 256 24 80 mhz p-44a adv478kp66 0 c to +70 c 256 24 66 mhz p-44a adv478kp50 0 c to +70 c 256 24 50 mhz p-44a adv478kp35 0 c to +70 c 256 24 35 mhz p-44a *p = plastic leaded chip carrier (plcc). warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv478/adv471 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v voltage on any digital pin . . . . gnd C 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . C55 c to +125 c storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . +150 c vapor phase soldering (1 minute) . . . . . . . . . . . . . . . . . 220 c ior, iob, iog to gnd 2 . . . . . . . . . . . . . . . . . . . 0 v to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. plcc pin configuration obsolete
adv478/adv471 C5C rev. b pin function description pin mnemonic function blank composite blank control input (ttl compatible). a logic zero drives the analog outputs to the blanking level as illustrated in tables iv and v. it is latched on the rising edge of clock. when blank is a logical zero, the pixel and overlay inputs are ignored setup setup control input. used to specify either a 0 ire (setup = gnd) or 7.5 ire (setup = v aa ) blanking pedestal. sync composite sync control input (ttl compatible). a logical zero on this input switches off a 40 ire current source on the analog outputs (see figures 3 and 4). sync does not override any other control or data input, as shown in tables iv and v; therefore, it should be asserted only during the blanking interval. it is latched on the rising edge of clock. clock clock input (ttl compatible). the rising edge of clock latches the p0Cp7, ol0Col3, sync , and blank inputs. it is typically the pixel clock rate of the video system. it is recommended that clock be driven by a dedi- cated ttl buffer. p0Cp7 pixel select inputs (ttl compatible). these inputs specify, on a pixel basis, which one of the 256 entries in the color palette ram is to be used to provide color information. they are latched on the rising edge of clock. p0 is the lsb. unused inputs should be connected to gnd. ol0Col3 overlay select inputs (ttl compatible). these inputs specify which palette is to be used to provide color informa- tion, as illustrated in table iii. when accessing the overlay palette, the p0Cp7 inputs are ignored. they are latched on the rising edge of clock. ol0 is the lsb. unused inputs should be connected to gnd. ior, iog, iob red, green, and blue current outputs. these high impedance current sources are capable of directly driving a doubly terminated 75 w coaxial cable (figures 5 and 6). i ref full-scale adjust control. note that the ire relationships in figures 3 and 4 are maintained, regardless of the full-scale output current. when using an external voltage reference (figure 5), a resistor (r set ) connected between this pin and gnd controls the magnitude of the full-scale video signal. the relationship between r set and the full-scale output current on each output is: r set ( w ) = k 1,000 v ref ( v )/ i out ( ma ) k is defined in the table below, along with corresponding r set values for doubly terminated 75 w loads. when using an external current reference (figure 6), the relationship between i ref and the full-scale output current on each output is: i ref ( ma ) = i out ( ma )/ k mode pedestal k r set ( v ) 6-bit 7.5 ire 3.170 147 8-bit 7.5 ire 3.195 147 6-bit 0 ire 3.000 147 8-bit 0 ire 3.025 147 comp compensation pin. if an external voltage reference is used (figure 5), this pin should be connected to opa. if an external current reference is used, this pin should be connected to i ref . a 0.1 m f ceramic capacitor must always be used to bypass this pin to v aa . v ref voltage reference input. if an external voltage reference is used (figure 5), it must supply this input with a 1.2 v (typical) reference. if an external current reference is used (figure 6), this pin should be left floating, except for the bypass capacitor. a 0.1 m f ceramic capacitor must always be used to decouple this input to v aa as shown in figures 5 and 6. opa reference amplifier output. if an external voltage reference is used (figure 5), this pin must be connected to comp. when using an external current reference (figure 6), this pin should be left floating. v aa analog power. all v aa pins must be connected to the analog power plane. gnd analog ground. all gnd pins must be connected to the ground plane. wr write control input (ttl compatible). d0Cd7 data is latched on the rising edge of wr , and rs0Crs2 are latched on the falling edge of wr during mpu write operations. see figure 1. obsolete
adv478/adv471 C6C rev. b pin function description (continued) pin mnemonic function rd read control input (ttl compatible). to read data from the device, rd must be a logical zero. rs0Crs2 are latched on the falling edge of rd during mpu read operations. rs0, rs1, rs2 register select inputs (ttl compatible). rs0Crs2 specify the type of read or write operation being performed as illustrated in tables i and ii. d0Cd7 data bus (ttl compatible). data is transferred into and out of the device over this 8-bit bidirectional data bus. d0 is the least significant bit. 8/ 6 8-bit/6-bit select input (ttl compatible). this control input specifies whether the mpu is reading and writing 8- bits (logical one) or 6-bits (logical zero) of color information each cycle. for 8-bit operation, d7 is the most sig- nificant data bit during color read/write cycles. for 6-bit operation, d5 is the most significant data bit during color read/write cycles (d6 and d7 are ignored during color write cycles and are logical zero during color read cycles). this control input is implemented only on the adv478. terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level which will shut off the pic- ture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three pri- mary colors of red, green and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs would be required, one for each color. composite sync signal (sync) the portion of the composite video signal which synchronizes the scanning process. composite video signal the video signal with or without setup, plus the composite sync signal. gray scale the discrete levels of video signal between reference black and reference white levels. an 8-bit dac contains 256 different lev- els while a 6-bit dac contains 64. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. setups the difference between the reference black level and the blank- ing level. sync level the peak level of the composite sync signal. video signal that portion of the composite video signal which varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion which may be visually observed. obsolete
adv478/adv471 C7C rev. b circuit description mpu interface as illustrated in the functional block diagram, the adv478 and adv471 support a standard mpu bus interface, allowing the mpu direct access to the color palette ram and overlay color registers. the rs0Crs2 select inputs specify whether the mpu is access- ing the address register, color palette ram, overlay registers or read mask register, as shown in table i. the 8-bit address reg- ister is used to address the color palette ram and overlay r egis- ters, eliminating the requirement for external address multiplexers. to write color data, the mpu writes to the address register (se- lecting ram or overlay write mode) with the address of the color palette ram location or overlay register to be modified. the mpu performs three successive write cycles (8 or 6 bits each of red, green and blue), using rs0Crs2 to select either the color palette ram or overlay registers. during the blue write cycle, the three bytes of color information are concat- enated into a 24-bit word (18-bit word for the adv471) and written to the location specified by the address register. the ad- dress register then increments to the next location which the mpu may modify by simply writing another sequence of red, green and blue data. table i. control input truth table rs2 rs1 rs0 addressed by mpu 0 0 0 address register (ram write mode) 0 1 1 address register (ram read mode) 0 0 1 color palette ram 0 1 0 pixel read mask register 1 0 0 address register (overlay write mode) 1 1 1 address register (overlay read mode) 1 0 l overlay registers 1 1 0 reserved to read color data, the mpu loads the address register (select- ing ram or overlay read mode) with the address of the color palette ram location or overlay register to be read. the mpu performs three successive read cycles (8 or 6 bits each of red, green and blue), using rs0Crs2 to select either the color pal- ette ram or overlay registers. following the blue read cycle, the address register increments to the next location which the mpu may read by simply reading another sequence of red, green and blue data. when accessing the color palette ram, the address register re- sets to 00h following a blue read or write cycle to ram loca- tion ffh. when accessing the overlay color registers, the address register increments following a blue read or write cycle. however, while accessing the overlay color registers, the four most significant bits of the address register (addr4-7) are ig- nored. the mpu interface operates asynchronously to the pixel clock. data transfers between the color palette ram/overlay registers and the color registers (r, g and b in the block diagram) are synchronized by internal logic and occur in the period between mpu accesses. as only one pixel clock cycle is required to complete the transfer, the color palette ram and overlay regis- ters may be accessed at any time with no noticeable disturbance on the display screen. to keep track of the red, green and blue read/write cycles, the address register has two additional bits (addra, addrb) that count modulo three, as shown in table ii. they are reset to zero when the mpu writes to the address register and are not reset to zero when the mpu reads the address register. the mpu does not have access to these bits. the other eight bits of the address register, incremented following a blue read or write cycle (addr0C7), are accessible to the mpu and are used to address color palette ram locations and overlay registers, as shown in table ii. addr0 is the lsb when the mpu is ac- cessing the ram or overlay registers. the mpu may read the address register at any time without modifying its contents or the existing read/write mode. figure 1 illustrates the mpu read/write timing. table ii. address register (addr) operation value rs2 rs1 rs0 addressed by mpu addra,b (counts modulo 3) 00 red value 01 green value 10 blue value addr0C7 (counts binary) 00hCffh 0 0 1 color palette ram xxxx 0000 1 0 1 reserved xxxx 0001 1 0 1 overlay color 1 xxxx 0010 1 0 1 overlay color 2 ???? ? ???? ? xxxx 1111 1 0 1 overlay color 15 obsolete
adv478/adv471 C8C rev. b adv478 data bus interface on the adv478, the 8/ 6 control input is used to specify whether the mpu is reading and writing 8 bits (8/ 6 = logical one) or 6 bits (8/ 6 = logical zero) of color information each cycle. for 8-bit operation, do is the lsb and d7 is the msb of color data. for 6-bit operation (and also when using the adv471), color data is contained on the lower six bits of the data bus, with d0 being the lsb and d5 the msb of color data. when writing color data, d6 and d7 are ignored. during color read cycles, d6 and d7 will be a logical zero. adv471 data bus interface color data is contained on the lower six bits of the data bus, with d0 being the lsb and d5 the msb of color data. when writing color data, d6 and d7 are ignored. during color read cycles, d6 and d7 will be a logical zero. frame buffer interface the p0Cp7 and ol0Col3 inputs are used to address the color palette ram and overlay registers, as shown in table iii. table iii. pixel and overlay control truth table (pixel read mask register = ffh) ol0Col3 p0Cp7 addressed by frame buffer 0h 00h color palette ram location 00h 0h 01h color palette ram location 01h ?? ? ?? ? 0h ffh color palette ram location ffh 1h xxh overlay color 1 2h xxh overlay color 2 ?? ? ?? ? fh xxh overlay color 15 fiqure 3. composite video output waveform (setup = v aa ) table iv. video output truth table (setup= v aa ) dac description i out (ma) 1 sync blank input data white level 26.67 1 1 ffh data data + 9.05 1 1 data data-sync data + 1.44 0 1 data black level 9.05 1 1 00h black-sync 1.44 0 1 00h blank level 7.62 1 0 xxh sync level 0 0 0 xxh notes 1 typical with full-scale iog = 26.67 ma, setup = v aa . external voltage or current reference adjusted for 26.67 ma full-scale output. obsolete
adv478/adv471 C9C rev. b the contents of the pixel read mask register, which may be ac- cessed by the mpu at any time, are bit-wise logically anded with the p0Cp7 inputs. bit d0 of the pixel read mask register corresponds to pixel input p0. the addressed location provides 24 bits (18 bits for the adv471) of color information to the three d/a converters. for additional information on pixel mask register, see applica- tion note animation using the pixel read mask register of the adv47x series of video ram-dacs (publication number e1316C15C10/89). the sync and blank inputs, also latched on the rising edge of clock to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, produc- ing the specific output levels required for video applications, as illustrated in figures 3 and 4. tables iv and v detail how the sync and blank inputs modify the output levels. the setup input is used to specify whether a 0 ire (setup = gnd) or 7.5 ire (setup = v aa ) blanking pedestal is to be used. the analog outputs of the adv478 and adv471 are capable of directly driving a 37.5 w load, such as a doubly terminated 75 w coaxial cable. figure 4. composite video output waveform (setup = gnd) table v. video output truth table (setup = gnd) dac description i out (ma) l sync blank input data white level 26.67 1 1 ffh data data+8.05 1 1 data data-sync data 0 1 data black level 8.05 1 1 00h black-sync 0 0 1 00h blank level 8.05 1 0 xxh sync level 0 0 0 xxh note 1 typical with full-scale iog= 26.67 ma, setup = gnd. external voltage or current reference adjusted for 26.67 ma full-scale output. obsolete
adv478/adv471 C10C rev. b pc board layout considerations pc board considerations the layout should be optimized for lowest noise on the adv478/ adv471 power and ground lines by shielding the digital inputs and pr oviding good decoupling. the lead length between groups of v aa and gnd pins should by minimized so as to minimize in- ductive ringing. ground planes the ground plane should encompass all adv478/adv471 ground pins, current/voltage reference circuitry, power supply bypass circuitry for the adv478/adv471, the analog output traces and all the digital signal traces leading up to the adv478/ adv471. power planes the adv478/adv471 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as il- lustrated in figures 5 and 6. this bead should be located within three inches of the adv478/adv471. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv478/adv471 power pins and current/voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with a 0.1 m f ceramic capacitor decoupling each of the two groups of v aa pins to gnd. these capacitors should be placed as close as possible to the device. it is important to note that while the adv478 and adv471 contain circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three terminal volt- age regulator for supplying power to the analog power plane. figure 5. typical connection diagram and component list (external voltage reference) obsolete
adv478/adv471 C11C rev. b digital signal interconnect the digital inputs to the adv478/adv471 should be isolated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv478/adv471 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv478/adv471 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. for maximum performance, the analog outputs should each have a 75 w load resistor connected to gnd. the connection between the current output and gnd should be as close as pos- sible to the adv478/adv471 to minimize reflections. note: additional information on pc board layout can be obtained in an application note entitled design and layout of a video graphics system for reduced emi from analog devices (publication note e1309C15C10/89). figure 6. typical connection diagram and component list (external current reference) rs-170 video generation for generation of rs-170 compatible video, it is recommended that the dac outputs be connected to a singly terminated 75 w load. if the adv478/adv471 is not driving a large capacitive load, there will be negligible difference in video quality between doubly terminated 75 w and singly terminated 75 w loads. if driving a large capacitive load (load rc> 1/(2 p f c )), it is rec- ommended that an output buffer (such as an ad848 or ad9617 with an unloaded gain>2) be used to drive a doubly terminated 75 w load. application information external voltage vs. current reference the adv478/adv471 is designed to have excellent perfor- mance using either an external voltage or current reference. the voltage reference design (figure 5) has the advantages of temperature compensation, simplicity, lower cost and provides excellent power supply rejection. the current reference design (figure 6) requires more components to provide adequate power supply rejection and temperature compensation (two transistors, three resistors and additional capacitors). obsolete
adv478/adv471 C12C rev. b outline dimensions dimensions shown in inches and (mm). 44-terminal plastic leaded chip carrier p-44a c1197C24C6/88 printed in u.s.a. obsolete

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